rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9012 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 high-speed 8-bit ttl a/d converter functional block diagram 256 255 128 127 2 1 d e c o d i n g l o g i c l a t c h r r r r/2 r/2 r r overflow inhibit analog in v ref ref mid v ref encode gnd hysteresis v s d 2 d 3 d 4 d 5 d 6 d 7 d 8 (msb) overflow ad9012 d 1 (lsb) v s features 100 msps encode rate very low input capacitance16 pf low power1 w ttl compatible outputs mil-std-883 compliant versions available applications radar guidance digital oscilloscopes/ate equipment laser/radar warning receivers digital radio electronic warfare (ecm, eccm, esm) communication/signal intelligence general description the ad9012 is an 8-bit, ultrahigh speed, analog-to-digital converter. the ad9012 is fabricated in an advanced bipolar process that allows operation at sampling rates up to one hundred megasamples/second. functionally, the ad9012 is comprised of 256 parallel comparator stages whose outputs are decoded to drive the ttl compatible output latches. the exceptionally wide large-signal analog input bandwidth of 160 mhz is due to an innovative comparator design and very close attention to device layout considerations. the wide input bandwidth of the ad9012 allows very accurate acquisition of high speed pulse inputs without an external track-and-hold. the com parator output decoding scheme minimizes false codes, which is critical to high speed linearity. the ad9012 is available in two grades: one with 0.5 lsb linearity and one with 0.75 lsb linearity. both versions are offered in an industrial grade, ?5 c to +85 c, packaged in a 28-lead dip and a 28-lead jlcc. the military temperature range devices, ?5 c to +125 c, are available in ceramic dip and lcc packages and are compliant to mil-std-883 class b. the ad9012 is available in versions compliant with mil-std- 883. refer to the analog devices military products databook or current ad9012/883b data sheet for detailed specifications.
rev. e C2C ad9012?pecifications test ad9012aq/aj ad9012bq/bj ad9012sq/se ad9012tq/te parameter temp level min typ max min typ max min typ max min typ max unit resolution 8 8 8 8 bits dc accuracy differential linearity 25 c i 0.6 0.75 0.4 0.5 0.6 0.75 0.4 0.5 lsb full vi 1.0 0.75 1.0 0.75 lsb integral linearity 25 c i 0.6 1.0 0.4 0.5 0.6 1.0 0.4 0.5 lsb full vi 1.2 1.2 1.2 1.2 lsb no missing codes full vi guaranteed guaranteed guaranteed guaranteed initial offset error top of reference ladder 25 c i 7 15 7 15 7 15 7 15 mv full vi 18 18 18 18 mv bottom of reference ladder 25 c i 6 10 6 10 6 10 6 10 mv full vi 13 13 13 13 mv offset drift coefficient full v 25 25 25 25 v/ c analog input input bias current 1 25 c i 60 200 60 200 60 200 60 200 a full vi 200 200 200 200 a input resistance 25 c i 25 200 25 200 25 200 25 200 k ? input capacitance 25 c iii 16 18 16 18 16 18 16 18 pf large signal bandwidth 2 25 c v 160 160 160 160 mhz analog input slew rate 3 25 c v 440 440 440 440 v/ s reference input reference ladder resistance 25 c vi 40 80 110 40 80 110 40 80 110 40 80 110 ? ladder temperature coefficient v 0.25 0.25 0.25 0.25 ? / c reference input bandwidth 25 c v 10 10 10 10 mhz dynamic performance conversion rate 25 c i 75 100 75 100 75 100 75 100 msps aperture delay 25 c v 3.8 3.8 3.8 3.8 ns aperture uncertainty (jitter) 25 c v 15 15 15 15 ps output delay (t pd ) 4, 5 25 c i 4 4.9 11 4 4.9 11 4 4.9 11 4 4.9 11 ns transient response 6 25 cv 8 8 8 8 ns overvoltage recovery time 7 25 cv 8 8 8 8 ns output rise time 4 25 c i 6.6 8.0 6.6 8.0 6.6 8.0 6.6 8.0 ns output fall time 4 25 c i 3.3 4.3 3.3 4.3 3.3 4.3 3.3 4.3 ns output time skew 4, 8 25 c v 3.0 3.0 3.0 3.0 ns encode input logic ??voltage 4 full vi 2.0 2.0 2.0 2.0 v logic ??voltage 4 full vi 0.8 0.8 0.8 0.8 v logic ??current full vi 250 250 250 250 a logic ??current full vi 400 400 400 400 a input capacitance 25 c v 2.5 2.5 2.5 2.5 pf encode pulsewidth (low) 9 25 c i 2.5 2.5 2.5 2.5 ns encode pulsewidth (high) 9 25 c i 2.5 2.5 2.5 2.5 ns overflow inhibit input 0 v input current full vi 200 250 200 250 200 250 200 250 a ac linearity 10 effective bits 11 25 c v 7.5 7.5 7.5 7.5 bits in-band harmonics dc to 1.23 mhz 25 c i 48 55 48 55 48 55 48 55 dbc dc to 9.3 mhz 25 c v 50 50 50 50 dbc dc to 19.3 mhz 25 c v 44 44 44 44 dbc signal-to-noise ratio 12 25 c i 46 47.6 46 47.6 46 47.6 46 47.6 dbc noise power ratio 13 25 c v 37 37 37 37 dbc digital output logic ??voltage full vi 2.4 2.4 2.4 2.4 v logic ??voltage full vi 0.4 0.4 0.4 0.4 v power supply 14 positive supply current (+5.0 v) 25 c i 33 45 33 45 33 45 33 45 ma full vi 48 48 48 48 ma supply current (?.2 v) 25 c i 152 179 152 179 152 179 152 179 ma full vi 191 191 191 191 ma nominal power dissipation 25 c v 955 955 955 955 mw reference ladder dissipation 25 c v 44 44 44 44 mw power supply rejection ratio 15 25 c i 0.85 2.5 0.85 2.5 0.8 2.5 0.8 2.5 mv/v electrical characteristics (+v s = +5.0 v; ? s = ?.2 v; differential reference voltage = 2.0 v; unless otherwise noted.)
rev. e C3C ad9012 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9012 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device notes 1 measured with analog input = 0 v. 2 measured by fft analysis where fundamental is ? dbc. 3 input slew rate derived from rise time (10% to 90%) of full-scale step input. 4 outputs terminated with two equivalent ?s00 type loads. (see load circuit.) 5 measured from encode into data out for lsb only. 6 for full-scale step input, 8-bit accuracy is attained in specified time. 7 recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage. 8 output time skew includes high-to-low and low-to-high transitions as well a s bit-to-bit time skew differences. 9 encode signal rise/fall times should be less than 30 ns for normal operation. 10 measured at 75 msps encode rate. harmonic data based on worst case harmonics. 11 analog input frequency = 1.23 mhz. 12 rms signal to rms noise, including harmonics with 1.23 mhz. analog input signal. 13 npr measured @ 0.5 mhz. noise source is 250 mw (rms) from 0.5 mhz to 8 mhz. 14 supplies should remain stable within 5% for normal operation. 15 measured at ?.2 v 5% and +5.0 v 5%. specifications subject to change without notice. absolute maximum ratings 1 positive supply voltage (+v s ) . . . . . . . . . . . . . . . . . . . . . . 6 v analog to digital supply voltage differential (? s ) . . . 0.5 v negative supply voltage (? s ) . . . . . . . . . . . . . . . . . . . . 6 v analog input voltage . . . . . . . . . . . . . . . . . . . . ? s to +0.5 v encode input voltage . . . . . . . . . . . . . . . . . ?.5 v to +5 v overflow inh input voltage . . . . . . . . . . . ?.2 v to 0 v reference input voltage (+v ref ? ref ) 2 . . . ?.5 v to +0.1 v differential reference voltage . . . . . . . . . . . . . . . . . . . . 2.1 v reference midpoint current . . . . . . . . . . . . . . . . . . . . 4 ma digital output current . . . . . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range ad9012aq/bq/aj/bj . . . . . . . . . . . . . . . ?5 c to +85 c ad9012se/sq/te/tq . . . . . . . . . . . . . ?5 c to +125 c storage temperature range . . . . . . . . . . . ?5 c to +150 c junction temperature 3 . . . . . . . . . . . . . . . . . . . . . . . . 150 c lead soldering temperature (10 sec) . . . . . . . . . . . . . 300 c notes 1 absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 +v ref ? ref under all circumstances. 3 maximum junction temperature (t j max) should not exceed 150 c for ceramic and plastic packages: t j = pd ( ja ) + t a pd ( jc ) + tc where pd = power dissipation ja = thermal impedance from junction to ambient ( c/w) jc = thermal impedance from junction to case ( c/w) t a = ambient temperature ( c) t c = case temperature ( c) typical thermal impedances are: ceramic dip ja = 42 c/w; jc = 10 c/w ceramic lcc ja = 50 c/w; jc = 15 c/w jlcc ja = 59 c/w; jc = 15 c/w. recommended operating conditions input voltage parameter min nominal max ? s ?.46 ?.20 ?.94 +v s +4.75 5.00 +5.25 +v ref ? ref 0.0 v +0.1 ? ref ?.1 ?.0 +v ref analog input ? ref +v ref v s ttl output 15pf 1k figure 1. load circuit explanation of test levels test level i 100% production tested. ii 100% production tested at 25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi all devices are 100% production tested at 25 c. 100% production tested at temperature extremes for extended temperature devices; guaranteed by design and characterization testing for industrial devices. ordering guide temperature package device linearity ranges options * ad9012aq 0.75 lsb ?5 c to +85 c q-28 ad9012bq 0.50 lsb ?5 c to +85 c q-28 ad9012aj 0.75 lsb ?5 c to +85 c j-28a ad9012bj 0.50 lsb ?5 c to +85 c j-28a ad9012sq 0.75 lsb ?5 c to +125 c q-28 ad9012se 0.75 lsb ?5 c to +125 c e-28a ad9012tq 0.50 lsb ?5 c to +125 c q-28 ad9012te 0.50 lsb ?5 c to +125 c e-28a * e = leadless ceramic chip carrier; j = ceramic leaded chip carrier; q = cerdip.
rev. e ad9012 C4C pin function descriptions pin # name description 1 1 digital +v s one of three positive digital supply pins (nominally +5.0 v). 1 2 overflow inh overflow inhibit controls the data output coding for overvoltage inputs (ain + v ref ). 1 3 hysteresis the hysteresis control voltage varies the comparator hysteresis from 0 mv to 10 mv, for a change from ?.2 v to ?.2 v at the hysteresis control pin. 1 4+v ref the most positive reference voltage for the internal resistor ladder. 1 5 analog input one of two analog input pins. both analog input pins should be connected together. 1 6 analog ground one of two analog ground pins. both analog ground pins should be connected together. 1 7 encode ttl level encode command input. encode is rising edge sensitive. 1 8 digital +v s one of three positive digital supply pins (nominally +5.0 v). 1 9 analog ground one of two analog ground pins. both analog ground pins should be connected together. 10 analog input one of two analog input pins. both analog inputs should be connected together. 11 ? ref the most negative reference voltage for the internal resistor ladder. 12 ref mid the midpoint tap on the internal resistor ladder. 13 digital +v s one of three positive digital supply pins (nominally +5.0 v). 14 digital ? s one of two negative digital supply pins (nominally ?.2 v). both digital supply pins should be connected together. 15 d 1 (lsb) digital data output. d 1 (lsb) is the least significant bit of the digital output word. 16?9 d 2 ? 5 digital data output. 20 digital ground one of two digital ground pins. both digital grounds pins should be connected together. 21, 22 analog ? s one of two negative analog supply pins (nominally ?.2 v). both analog supply pins should be connected together. 23 digital ground one of two digital ground pins. both digital ground pins should be connected together. 24, 25 d 6 , d 7 digital data output. 26 d 8 (msb) digital data output d 8 (msb) is the most significant bit of the digital output word. 27 overflow overflow data output. logic high indicates an input overvoltage (v in > + v ref ), if overflow inhibit is enabled (overflow enabled, floating). see overflow inhibit. 28 digital ? s one of two negative digital supply pins (nominally ?.2 v). both digital supply pins should be connected together. analog overflow enabled (floating) overflow inhibited (gnd) input of d l d 2 d 3 d 4 d 5 d 6 d 7 d 8 of d l d 2 d 3 d 4 d 5 d 6 d 7 d 8 v in + v ref 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 v in < + v ref 0 x x x x x x x x 0 x x x x x x x x pin configurations top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad9012 digital v s + ref mid ? ref analog input analog ground digital v s + digital v s + overflow inh hysteresis +v ref encode analog ground analog input d 1 (lsb) d 2 d 3 d 4 d 5 digital ground analog v s digital v s overflow d 8 (msb) d 7 analog v s digital ground d 6 digital v s top view (not to scale) 28 27 1 2 3 426 25 21 22 23 24 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 d 7 d 6 digital ground analog v s analog v s d 5 analog input analog ground encode digital v s + analog input v ref +v ref hysteresis overflow inh digital v s + digital v s overflow d 8 (msb) ref mid digital v s + digital v s d 1 (lsb) d 2 d 3 d 4 ad9012 digital ground analog ground
rev. e C5C ad9012 aperture delay analog input encode output data n n + 1 n + 2 n 1 n + 1 n t pd figure 2. timing diagram v ref r r/2 r/2 r v ref 5.2v 256 comparator cells ref mid analog input encode 5.0v digital outputs 5.0v figure 3. input output circuits die layout and mechanical information die dimensions . . . . . . . . . . . . . . . . 111 123 15 ( 2) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? s passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nitride die attach . . . . . . . . . . . . . . . . . . . . gold eutectic (ceramic) epoxy (plastic) bond wire . . . . . . . . . . . . . 1?.3 mil gold; gold ball bonding all resistors 5% all capacitors 20% all supply voltages 5% d 1 (lsb) d 2 d 3 d 4 d 5 d 6 d 7 overflow ain encode v ref v h +v ref ad1 ad2 2.0v digital ground analog ground 0.1 f 5.2v +5.0v v s +v s 0.1 f 100 510 d 8 (msb) one jumper per board option #1 (static) ad1 = 2.0v; ad2 = +2.4v option #2 (dynamic) see waveforms ad9012 0v 2v +2.4v +0.4v 640 s 5 s ad1 ad2 1k 1k 1k 1k 1k 1k 1k 1k 1k d 1 (lsb) load resistors figure 4. burn-in diagram
rev. e ad9012 C6C application information the ad9012 is compatible with all standard ttl logic fami lies. however, to operate at the highest encode rates, the supporting logic around the ad9012 will need to be equally fast. two possible choices are the as and the als families. whiche ver of the ttl logic families is used, special care must be exercised to keep digital switching noise away from the analog circuits around the ad9012. the two most critical items are the digital supply lines and the digital ground return. the input capacitance of the ad9012 is an exceptionally low 16 pf. this allows the use of a wide range of input amplifiers, both hybrid and monolithic. to take full advantage of the 160 mhz input bandwidth of the ad9012, a hybrid amplifier like the ad9610/ad9611 will be required. for those applica- tions that do not require the full input bandwidth of the ad9012, some of the more traditional monolithic amplifiers, like the ad846, should work very well. overall performance with monolithic amplifiers can be improved by inserting a 40 ? resis tor in series with the amplifier output. the output data is buffered through the ttl compatible out- put latches. in addition to the latch propagation delay (t pd ), all data is delayed by one clock cycle, before becoming available at the outputs. both the analog-to-digital conversion cycle and the data transfer to the output latches are triggered on the rising edge of the ttl-compatible encode signal (see timing diagram). the ad9012 also incorporates a hysteresis control pin which provides from 0 mv to 10 mv of additional hysteresis in the comparator input stages. adjustments in the hysteresis control voltage may help to improve noise immunity and overall performance in harsh environments. the overflow inhibit pin of the ad9012 determines how the converter handles overrange inputs (ain + v ref ). in the ?nabled?state (floating at ?.2 v), the overflow out- put will be at logic high and all other outputs will be at logic low for overrange inputs (return-to-zero operation). in the ?nhibited?state (tied to ground), the overflow output will be at logic low for overrange inputs, and all other digital out- puts will be at logic high (nonreturn-to-zero operation). the ad9012 provides outstanding error rate performance. this is due to tight control of comparator offset matching and a fault tolerant decoding stage. additional improvements in error rate are possible through the addition of hysteresis (see hysteresis control pin). this level of performance is extremely impo rtant in fault sensitive applications such as digital radio (qam). dramatic improvements in comparator design and construction give the ad9012 excellent dynamic characteristics, namely snr (signal-to-noise ratio). the 160 mhz input bandwidth and low error rate performance give the ad9012 an snr of 47 db with a 1.23 mhz input. high snr performance is particularly im por- tant in broadcast video applications where signals may pass through the converter several times before the processing is complete. pulse signature analysis, commonly performed in advanced radar receivers, is another area that is especially dependent on high quality dynamic performance. layout suggestions designs using the ad9012, like all high-speed devices, must follow a few basic layout rules to insure optimum performance. essentially, these guidelines are meant to avoid many of the problems associated with high-speed designs. the first require- ment is for a substantial ground plane around and under the ad9012. separate ground plane areas for the digital and analog components may be useful, but the separate grounds should be connected together at the ad9012 to avoid the effects of ?round loop?currents. the second area that requires an extra degree of attention involves the three reference inputs, +v ref , ref mid , and ? ref . the +v ref input and the ? ref input should both be driven from a low impedance source (note that the +v ref input is typically tied to analog ground). a low drift amplifier should provide satisfactory results, even over an extended temperature range. adjustments at the ref mid input may be useful in im prov- ing the integral linearity by correcting any reference ladder skews. the reference inputs should be adequately decoupled to ground through 0.1 f chip capacitors to limit the effects of system noise on conversion accuracy. the power supply pins must also be decoupled to ground to improve noise immunity; 0.1 f and 0.01 f chip capacitors should be very effective. the analog input signal is brought into the ad9012 through two separate input pins. it is very important that the two input pins be driven symmetrically with equal length electrical connections. otherwise, aperture delay errors may degrade converter performance at high frequencies. 100 2n3906 overflow d 8 (msb) d 7 d 6 d 5 d 4 d 3 d 2 d 1 (lsb) 5.2v +5.0v 0.01 f 0.1 f 0.01 f encode a in a in v ref +v ref 0.1 f 10 0.1 f ad741 ad9611 40 ad9012 equal distance 50 ttl encode input analog input (0 to +2v) 1k 4k 15v 1.5k 50 0.1 f nyquest filter figure 5. typical application
rev. e ad9012 C7C 10 overflow d 8 (msb) d 7 d 6 d 5 d 4 d 3 d 2 d 1 (lsb) 5.2v +5.0v 0.01 f 0.1 f 0.01 f encode a in a in v ref +v ref 0.1 f 100 ad741 hos200 ad9012 equal distance ttl encode input 240 5.2v 50 500 0.1 f latch 74as843 clk 10124 10124 25 pin d connector 1k 1k 74as04 overflow inh 560 1k 5.2v 0.1 f hysteresis ref mid 0.1 f 240 2n3906 160 0.01 f 0.1 f 82 1n747 100 2n3906 ad642 analog input (2v p-p max) 50 100 430 430 linearity output (error waveform) ad642 reconstructed output 37.5 50 note: 10124, ecl outputs, should be terminated to 2v with 100 registers. ad9768 figure 6. evaluation circuit analog input frequency mhz 65 1 dbc 60 55 50 45 40 35 30 100 3rd harmonic 2nd harmonic snr * 10 * with harmonics input = 0.1db below full scale encode rate = 75msps 70 figure 7. dynamic performance
rev. e C8C c00547cC0C7/01(e) printed in u.s.a. ad9012 outline dimensions dimensions shown in inches and (mm). 28-lead jlcc (j-28a) 0.0066 (0.167) 0.0054 (0.137) 0.171 (4.34) max 0.044 (1.118) 0.034 (0.864) 0.030 (0.762) 0.026 (0.660) 0.021 (0.534) 0.017 (0.432) 0.430 (10.922) 0.410 (10.414) 0.112 (1.702) 0.092 (1.194) bottom view 0.025 (0.635) 0.019 (0.483) pin 1 top view (pins down) 4 5 26 25 19 18 12 11 0.050 (1.27) bsc 0.300 (7.62) typ sq 0.498 (12.649) 0.478 (12.141) sq 0.456 (11.582) 0.444 (11.278) 28-lead cerdip (q-28) 28 114 15 0.525 (13.33) 0.515 (13.08) 1.490 (37.84) max pin 1 15 0 0.62 (15.74) 0.59 (14.93) 0.012 (0.305) 0.008 (0.203) seating plane 0.22 (5.59) max 0.18 (4.57) max 0.02 (0.5) 0.016 (0.406) 0.11 (2.79) 0.099 (2.28) 0.06 (1.52) 0.05 (1.27) 0.125 (3.175) min glass sealant lead no. 1 identified by dot or notch leads are solder or tin plated kovar or alloy 42 28-terminal leadless chip carrier (e-28a) 0.100 (2.54) 1 0.064 (1.63) 1 28 5 11 12 18 26 19 4 25 bottom view 0.028 (0.71) 0.022 (0.56) 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) ref 0.020 45 (0.51 45 ) ref pin 1 index 0.040 45 (1.02 45 ) ref 3 plcs 0.055 (1.40) 0.045 (1.14) 0.458 (11.63) 2 0.442 (11.23) top view notes 1 this dimension controls the overall package thickness. 2 applies to all four sides. terminals are gold plated or solder dipped.
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